`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:00:27 11/06/2012 
// Design Name: 
// Module Name:    DOWNSHIFT_ROM_CTR 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module DOWNSHIFT_ROM_CTR #(parameter STEP=34, LOG_LEN=7, LEN=96, WIDTH=16, OFFSET=0)
(
	 input clk,
	 input rst,
	 input signed[WIDTH-1:0] in_data,
	 input signed[WIDTH-1:0] in_cos,
	 input signed [WIDTH-1:0] in_sin,
    output reg[LOG_LEN-1:0] addr_cos,
    output reg[LOG_LEN-1:0] addr_sin,
	 output reg signed[WIDTH+WIDTH-1:0] out_r,
    output reg signed[WIDTH+WIDTH-1:0] out_i
    );
	 
	 reg[LOG_LEN-1:0] count;
	 
	 always @(posedge clk or negedge rst)
		if(!rst)
			count <= 0;
		else if(count + STEP < LEN)
			count <= count + STEP;
		else
			count <= count + STEP - LEN;
			
	always @(posedge clk or negedge rst)
		if(!rst)
		begin
			addr_cos <= 0;
			addr_sin <= 0;
		end
		else
		begin
			addr_cos <= count;
			addr_sin <= count;
		end
		
	always @(posedge clk or negedge rst)
		if(!rst)
		begin
			out_r <= 0;
			out_i <= 0;
		end
		else
		begin
			out_r <= in_data * in_cos;
			out_i <= in_data * in_sin;
		end

endmodule
